A 10 GIPS SIMD processor for PC-based real-time vision applications - Architecture, algorithm implementation and language support

被引：16
|
作者：
Fujita, Y
Kyo, S
Yamashita, N
Okazaki, S
机构：
来源：
CAMP'97 - FOURTH IEEE INTERNATIONAL WORKSHOP ON COMPUTER ARCHITECTURE FOR MACHINE PERCEPTION, PROCEEDINGS | 1997年
关键词：
D O I：
10.1109/CAMP.1997.631885
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper describes hardware implementation and software environment of a one-dimensional SIMD processor. IMAP-VISION. IMAP-VISION board is a single-slot PCI-bus board designed for PG-based real-time vision applications. The SIMD processor consists of 256 8-bit linear processor array and has 10.24 GIPS peak performance. In this paper, some detailed algorithm implementations, those which make else of IMAP-VISION special functions, are described, as well as IMAP-VISION architecture, hardware implementation, performance figures and software environment including high-level language 1DC and graphical user interface.
引用
收藏
页码：22 / 32
页数：3
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