Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes

被引：0

作者：

Zhang, Peng-Wei ^{[1
,2
]}

Jiang, Sheng ^{[1
]}

Lau, Francis C. M. ^{[1
]}

Sham, Chiu-Wing ^{[3
]}

机构：

[1] Hong Kong Polytech Univ, Dept Elect & Informat Engn, Future Wireless Networks & IoT Focusing Area, Hong Kong, Peoples R China

[2] Huawei Technol Ltd, Chengdu 611731, Peoples R China

[3] Univ Auckland, Dept Comp Sci, Auckland 1010, New Zealand

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2022年 / 69卷 / 12期

关键词：

Hardware design; layered decoding; PLDPC-Hadamard code; PARITY-CHECK CODES; QC-LDPC DECODER; EFFICIENT; DESIGN; RESOLUTION; ALGORITHM;

D O I：

10.1109/TCSI.2022.3200687

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Protograph-based low-density parity-check Hadamard codes (PLDPC-HCs) are a new type of ultimate-Shannon-limit-approaching codes. In this paper, we propose a hardware architecture for the PLDPC-HC layered decoders. The decoders consist mainly of random address memories, Hadamard sub-decoders and control logics. Two types of pipelined structures are presented and the latency and throughput of these two structures are derived. Implementation of the decoder design on an FPGA board shows that a throughput of 1.48 Gbps is achieved with a bit error rate (BER) of 10(-5) at around E-b/N-0 = -0.40 dB. The decoder can also achieve the same BER at E-b/N-0 = -1.14 dB with a reduced throughput of 0.20 Gbps.

引用

页码：5325 / 5338

页数：14

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