Direct Cu Plating of High Aspect Ratio Through Silicon Vias (TSVs) with Ru Seed on 300 mm Wafer

被引：0
|
作者：
Wafula, Fred [1 ]
Pattanaik, Gyanaranjan [1 ]
Enloe, Jack [1 ]
Hummler, Klaus [2 ]
Sapp, Brian [2 ]
机构：
[1] Atotech USA Inc, Albany, NY 12203 USA
[2] SEMATECH, Albany, NY 12203 USA
来源：
2014 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE / ADVANCED METALLIZATION CONFERENCE (IITC/AMC) | 2014年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, physical and electrical results of full wafer direct Cu plating of 2x40 mu m TSVs with thin Ru seed are presented. Physical vapor deposition of about 100 nm Cu in the field is shown to improve plating non-uniformity across the structured wafer. TSV plating using Atotech's TSV III chemistry results in bottom-up growth with strong TSV sidewall suppression and void free TSV fill. Early results for in-line electrical test and voltage ramp dielectric breakdown reliability testing are discussed.
引用
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页码：143 / 145
页数：3
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