The hardware structure design of perceptron with FPGA implementation

被引:0
|
作者
Wang, QR [1 ]
Yi, B [1 ]
Xie, Y [1 ]
Liu, BR [1 ]
机构
[1] Guangdong Univ Technol, Fac Automat, Guangzhou 510080, Peoples R China
来源
2003 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN AND CYBERNETICS, VOLS 1-5, CONFERENCE PROCEEDINGS | 2003年
关键词
neural networks; perceptron; FPGA; VHDL; Top-Down;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Most commonly, neural networks's models or algorithms are simulated and implemented by computer programming in neural networks theory research. But in many practical applications, it is necessary to consider essential issues such as hardware implementation. Specific application of neural networks hardware has the advantages of high speed, small in size, good performance and low cost. Thus, the implementation of high performance neural networks hardware is the final target in some actual applications. In this paper, a hardware structure of single perceptron that serves as the basic nerve cell and its implementation method with FPGA is introduced. It is based on VLSI implementation approach for the standard neural networks. The method proposed is a primary discussion and research for the hardware implementation of artificial neural networks.
引用
收藏
页码:762 / 767
页数:6
相关论文
共 50 条
  • [41] FPGA design and implementation for EIT data acquisition
    Yue, Xicai
    McLeod, Chris
    PHYSIOLOGICAL MEASUREMENT, 2008, 29 (10) : 1233 - 1246
  • [42] AES hardware implementation in FPGA for algorithm acceleration purpose
    Gielata, Artur
    Russek, Pawel
    Wiatr, Kazimierz
    ICSES 2008 INTERNATIONAL CONFERENCE ON SIGNALS AND ELECTRONIC SYSTEMS, CONFERENCE PROCEEDINGS, 2008, : 137 - 140
  • [43] An Efficient Hardware Implementation of Crystal-Dilithium on FPGA
    Wu, Zixuan
    Chen, Rongmao
    Wang, Yi
    Wang, Qiong
    Peng, Wei
    INFORMATION SECURITY AND PRIVACY, PT II, ACISP 2024, 2024, 14896 : 64 - 83
  • [44] Hardware Implementation of Cyclic Codes Error Correction on FPGA
    Van-Tinh Nguyen
    Van-Lan Dao
    Thi-Thanh-Dung Phan
    2016 3RD NATIONAL FOUNDATION FOR SCIENCE AND TECHNOLOGY DEVELOPMENT CONFERENCE ON INFORMATION AND COMPUTER SCIENCE (NICS), 2016, : 97 - 100
  • [45] FPGA-orthopoly: a hardware implementation of orthogonal polynomials
    Asghari, M.
    Rasanan, A. H. Hadian
    Gorgin, S.
    Rahmati, D.
    Parand, K.
    ENGINEERING WITH COMPUTERS, 2023, 39 (03) : 2257 - 2276
  • [46] FPGA Implementation of IP Packet Header Parsing Hardware
    Efnusheva, Danijela
    Tentov, Aristotel
    Cholakoska, Ana
    Kalendar, Marija
    PROCEEDINGS OF THE 5TH INTERNATIONAL CONFERENCE ON APPLIED INNOVATIONS IN IT, 2017, 5 : 33 - 41
  • [47] Hardware Implementation of the PBAS Foreground Detection Method in FPGA
    Kryjak, Tomasz
    Komorkiewicz, Mateusz
    Gorgon, Marek
    MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, MIXDES 2013, 2013, : 479 - 484
  • [48] The FPGA Hardware Implementation of the Gated Recurrent Unit Architecture
    Zaghloul, Zaghloul Saad
    Elsayed, Nelly
    SOUTHEASTCON 2021, 2021, : 366 - 370
  • [49] Design, Hardware Implementation on FPGA and Performance Analysis of Three Chaos-Based Stream Ciphers
    Dridi, Fethi
    El Assad, Safwan
    Youssef, Wajih El Hadj
    Machhout, Mohsen
    FRACTAL AND FRACTIONAL, 2023, 7 (02)
  • [50] A Software-Hardware Mixed Design for the FPGA Implementation of the Real-Time Edge Detection
    El Houari, Kobzili
    Cherrad, Benbouchama
    Zohir, Irki
    IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN AND CYBERNETICS (SMC 2010), 2010,