All-analytic surface potential model for SOI MOSFETs

被引:18
作者
Yu, YS
Kim, SH
Hwang, SW
Ahn, D
机构
[1] Hankyong Natl Univ, Dept Informat & Control Engn, Ansong 456749, Gyeonggi, South Korea
[2] Korea Univ, Dept Elect & Comp Engn, Seoul 136075, South Korea
[3] Univ Seoul, Inst Quantum Informat Proc & Syst, Seoul 130743, South Korea
来源
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS | 2005年 / 152卷 / 02期
关键词
D O I
10.1049/ip-cds:20041110
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An all-analytic front surface potential model for SOI MOSFETs is presented, which is not only obtained from previously developed models, but is also derived from assumptions made for approximations of various operating regions. A single formula for the drain current is obtained by smoothly connecting the analytic solutions for various operating regions. The formula can be used from accumulation to strong inversion and from the partially depleted (PD) region to the fully depleted (FD) region. Owing to the one-dimensional nature of the model, the critical gate bias at which the transition occurs between the PD and FD regions can also be obtained analytically. Most secondary effects can easily be included in the current model and the model accurately reproduces numerical and experimental results. No discontinuity in the derivative of the surface potential is found and the newly introduced parameters used in the smoothing functions do not depend strongly on the process parameters.
引用
收藏
页码:183 / 188
页数:6
相关论文
共 14 条
[1]   MODELING THE POLYSILICON DEPLETION EFFECT AND ITS IMPACT ON SUBMICROMETER CMOS CIRCUIT PERFORMANCE [J].
ARORA, ND ;
RIOS, R ;
HUANG, CL .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (05) :935-943
[2]   An analytical CAD kink effect model of partially-depleted SOI NMOS devices operating in strong inversion [J].
Chen, SS ;
Kuo, JB .
SOLID-STATE ELECTRONICS, 1997, 41 (03) :447-458
[3]   AN ANALYTICAL DRAIN CURRENT MODEL CONSIDERING BOTH ELECTRON AND LATTICE TEMPERATURES SIMULTANEOUSLY FOR DEEP-SUBMICRON ULTRATHIN SOI NMOS DEVICES WITH SELF-HEATING [J].
CHEN, YG ;
MA, SY ;
KUO, JB ;
YU, ZP ;
DUTTON, RW .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (05) :899-906
[4]  
COLINGE JP, 1997, SILICON INSULATOR TE
[5]   MODELING THE IV CHARACTERISTICS OF FULLY DEPLETED SUBMICROMETER SOI MOSFETS [J].
HSIAO, TC ;
KISTLER, NA ;
WOO, JCS .
IEEE ELECTRON DEVICE LETTERS, 1994, 15 (02) :45-47
[6]  
HU C, 1999, BSIMSOI V2 1 MOSFET
[7]   A unified analytical fully depleted and partially depleted SOI MOSFET model [J].
Jang, SL ;
Huang, BR ;
Ju, JJ .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (09) :1872-1876
[8]  
Kuo J.B., 1998, SOI CMOS Technology BT-CMOS VLSI Engineering: Silicon-on-Insulator (SOI), P15, DOI [10.1007/978-1-4757-2823-1_2, DOI 10.1007/978-1-4757-2823-1_2]
[9]   A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation [J].
Lee, MSL ;
Tenbroek, BN ;
Redman-White, W ;
Benson, J ;
Uren, MJ .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (01) :110-121
[10]  
Miura-Mattausch M, 2001, IEEE CIRCUITS DEVICE, V17, P29, DOI 10.1109/101.968914