Implementation of high-k and metal gate materials for the 45 nm node and beyond:: gate patterning development

被引：12

作者：

Beckx, S ^{[1
]}

Demand, M ^{[1
]}

Locorotondo, S ^{[1
]}

Henson, K ^{[1
]}

Claes, M ^{[1
]}

Paraschiv, V ^{[1
]}

Shamiryan, D ^{[1
]}

Jaenen, P ^{[1
]}

Boullart, W ^{[1
]}

Degendt, S ^{[1
]}

Biesemans, S ^{[1
]}

Vanhaelemeersch, S ^{[1
]}

Vertommen, J ^{[1
]}

Coenegrachts, B ^{[1
]}

机构：

[1] IMEC, Lam Res Corp, B-3001 Heverlee, Belgium

来源：

MICROELECTRONICS RELIABILITY | 2005年 / 45卷 / 5-6期

关键词：

D O I：

10.1016/j.microrel.2004.11.005

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report on gate patterning development for the 45 nm node and beyond. Both poly-Si and different metal gates in combination with medium-k and high-k dielectrics have been defined. Source/drain silicon recess has been characterized for different stacks, yielding optimised processes for all investigated. Using hardmask based etching allowed us to produce sub-20 nm poly-Si and metal gates. Implementation of advanced metal gate patterning in already developed multigate field effect transistors (MuGFET) devices has been demonstrated. (c) 2004 Elsevier Ltd. All rights reserved.

引用

页码：1007 / 1011

页数：5

共 4 条

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Zhao, C ;

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[2]

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[3]

HENSON K, 2004, NMOS TRANSISTORS MET, P851

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Vitale, SA ;

Smith, BA .

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