An 1 lb 1GS/s Time-Interleaved ADC with Linearity Enhanced TM

被引：0

作者：

Zhu, Yan ^{[1
]}

Chan, Chi-Hang ^{[1
]}

Martins, R. P. ^{[1
]}

机构：

[1] Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Macau, Peoples R China

来源：

2018 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC): PROCEEDINGS OF TECHNICAL PAPERS | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a IGS/s 11 bit 4 x Time-Interleaved (TI) ADC employing the proposed Track-and-Hold (T/H) to enhance the sampling linearity and avoid timing skews. A dual auxiliary Source-Follower (SF) Till provides signal double boosting to suppress the sampling distortion while maintaining good power efficiency. We present a dynamic SF-based switch boosting technique, providing a fast signal boost up and less signal attenuation to maximize the tracking duration and Vg, of the sampling switch. A prototype in 65nm CMOS achieves SNDR of 55.8dB @Nyquist input and ERBW up to 2xNyquist input with total 22mW power.

引用

页数：2