An illustrated methodology for analysis of error tolerance

被引：26
|
作者：
Breuer, Melvin A. [1 ]
Zhu, Haiyang [2 ]
机构：
[1] Univ So Calif, Los Angeles, CA 90089 USA
[2] Analog Devices Inc, Norwood, MA 02062 USA
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2008年 / 25卷 / 02期
基金：
美国国家科学基金会;
关键词：
Defective flash memory; Error tolerance; Mean opinion score; Telephone answering machine; Yield;
D O I：
10.1109/MDT.2008.30
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Noise, defects, and process variations are likely to cause very unpredictable circuit performance in future billion-transistor dies, hence decreasing raw yield. Error tolerance is one of several techniques that can increase effective yield. This article presents a methodology for analyzing the suitability of error tolerance for a particular application and implementation. The methodology, illustrated here by a digital telephone-answering device, is applicable to a broad class of systems.
引用
收藏
页码：168 / 177
页数：10
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