Design of a Frequency Synthesizer with Digital Calibration and Spur Reduction Technology for Communications networks Application

Chip Design of a frequency synthesizer with digital calibration and spur reduction method operating at 5.0-GHz band is proposed and fabricated in TSMC 0.18-um CMOS process. The proposed PLL with digital calibration reduces VCO gain, Kvco to achieve better phase noise and spur performance in systems networks and architectures for high end computing. The proposed CP reduces phase error and spur at the PFD. When the proposed CP is used, the measured reference spur is reduced to -59.1 dBm. Measurement results show that digital supply voltage of 1.8 V, VCO output frequency is from 4.9 similar to 5.12 GHz, and frequency synthesizer phase noise is about -114.82dBc/Hz at 1MHz. Power consumption is 20.1 mW. Including pads, the chip area is 0.83 mm(2) for applications of computer, and sensor networks.