An ultra high-speed FFT processor

被引：0

作者：

Zhong, K ^{[1
]}

He, H ^{[1
]}

Zhu, GX ^{[1
]}

机构：

[1] Huazhong Univ Sci & Technol, Dept Elect & Informat Engn, Wuhan 430074, Peoples R China

来源：

SCS 2003: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS | 2003年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents an implementation of an ultra high-speed FFT processor which can process input data of 800MHz sample rate. In order to meet such an extremely real-time requirement, high-speed differential I/O interfaces (LVDS) and dedicated parallel-pipelined radix-8 architecture are adopted. Implemented in a FPGA device, the processor can operate at 115MHz and compute a 4096-point complex FFT in 5us. To reduce power consumption, currently, the chip is being migrated to 0.18 mu m CMOS technology.

引用

页码：37 / 40

页数：4

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