Dual input switched-capacitor-based single-phase hybrid boost multilevel inverter topology with reduced number of components

被引:49
|
作者
Rawa, Muhyaddin [1 ,2 ]
Siddique, Marif Daula [3 ]
Mekhilef, Saad [1 ,3 ,4 ]
Shah, Noraisyah [3 ]
Bassi, Hussain [1 ,5 ]
Seyedmahmoudian, Mehdi [4 ]
Horan, Ben [6 ]
Stojcevski, Alex [4 ]
机构
[1] King Abdulaziz Univ, Ctr Res Excellence Renewable Energy & Power Syst, Jeddah 21589, Saudi Arabia
[2] King Abdulaziz Univ, Fac Engn, Dept Elect & Comp Engn, Jeddah, Saudi Arabia
[3] Univ Malaya, Dept Elect Engn, Power Elect & Renewable Energy Res Lab, Kuala Lumpur 50603, Malaysia
[4] Swinburne Univ Technol, Fac Sci Engn & Technol, Sch Software & Elect Engn, Hawthorn, Vic 3122, Australia
[5] King Abdulaziz Univ, Fac Engn, Dept Elect Engn, Rabigh 25732, Saudi Arabia
[6] Deakin Univ, Sch Engn, Geelong, Vic 3216, Australia
关键词
CONVERTER; VOLTAGE;
D O I
10.1049/iet-pel.2019.0826
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new switched-capacitor-based topology with features of boosting and self-voltage balancing of the capacitor has been proposed in this study. The proposed multilevel inverter topology uses two isolated dc voltage sources with a switched-capacitor to produce 11 levels across the load. In this study, two different modes of the selection of dc voltage sources have been discussed for the proposed topology. Furthermore, the generalised structure of the proposed boost topology has also been discussed. Quantitative comparison with several topologies has been carried out to set the benchmark of the proposed topology. Selective harmonic elimination pulse width modulation technique has been adopted to improve the performance of the suggested topology. The power loss analysis of the proposed topology gives the maximum efficiency of 96.5% at the output power of 100 W and has an efficiency value of 95.3% at the output power of 500 W. The proposed topology has been simulated using PLECS and the simulation results have been verifying using an experimental prototype. The proposed topology has been tested for the different types of load and changes in the modulation index. The experimental results have verified the feasibility of the proposed topology.
引用
收藏
页码:881 / 891
页数:11
相关论文
共 50 条
  • [31] Switched-Capacitor-Based Multi-Source Multilevel Inverter With Reduced Part Count
    Singh, Deepak
    Sandeep, N.
    IEEE Journal of Emerging and Selected Topics in Industrial Electronics, 2023, 4 (03): : 718 - 724
  • [32] Single-Phase 9L Switched-Capacitor Boost Multilevel Inverter (9L-SC-BMLI) Topology
    Daula Siddique, Marif
    Aslam Husain, Mohammed
    Iqbal, Atif
    Mekhilef, Saad
    Riyaz, Ahmed
    IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 2023, 59 (01) : 994 - 1001
  • [33] Reduced Switch Quadruple Boost Switched Capacitor-based Multilevel Inverter
    Panda, Kaibalya Prasad
    Babu, Narendra P.
    Bisoyi, Sanjiba Kumar
    Panda, Gayadhar
    2020 3RD INTERNATIONAL CONFERENCE ON ENERGY, POWER AND ENVIRONMENT: TOWARDS CLEAN ENERGY TECHNOLOGIES (ICEPE 2020), 2021,
  • [34] Switched capacitor-based quadruple boost multilevel inverter topology with reduced switch count and its extension
    Murugan, Oorappan G.
    Pandarinathan, Sivaraman
    Dhas, B. Goldvin Sugirtha
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2024, 111 (07) : 1230 - 1252
  • [35] Single-Source Switched-Capacitor-Based Multilevel Inverter (S3CMLI) and Its Horizontal/Vertical Extension with Reduced Components
    Murugan, Oorappan G.
    Arumugam, Jeevanandham
    IRANIAN JOURNAL OF SCIENCE AND TECHNOLOGY-TRANSACTIONS OF ELECTRICAL ENGINEERING, 2023, 47 (01) : 337 - 353
  • [36] A 3-Φ switched-capacitor-based multilevel inverter with reduced voltage stress and part count
    Jena, Kasinath
    Gupta, Krishna Kumar
    Kumar, Dhananjay
    Dewangan, Niraj Kumar
    Kabat, Subash Ranjan
    ELECTRICAL ENGINEERING, 2024, 106 (03) : 2679 - 2690
  • [37] Single-Source Switched-Capacitor-Based Multilevel Inverter (S3CMLI) and Its Horizontal/Vertical Extension with Reduced Components
    Oorappan G. Murugan
    Jeevanandham Arumugam
    Iranian Journal of Science and Technology, Transactions of Electrical Engineering, 2023, 47 : 337 - 353
  • [38] A new single-phase cascaded multilevel inverter topology with reduced number of switches and voltage stress
    Siddique, Marif Daula
    Mekhilef, Saad
    Shah, Noraisyah Mohamed
    Sarwar, Adil
    Memon, Mudasir Ahmed
    INTERNATIONAL TRANSACTIONS ON ELECTRICAL ENERGY SYSTEMS, 2020, 30 (02):
  • [39] A Novel 17-Level Reduced Component Single DC Switched-Capacitor-Based Inverter With Reduced Input Spike Current
    Singh, Ashutosh Kumar
    Mandal, Rajib Kumar
    IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, 2022, 10 (05) : 6045 - 6056
  • [40] A Novel Dual-Input Switched-Capacitor Based 27-Level Boost Inverter Topology
    Khatoonabad, Saeid Deliri
    Varesi, Kazem
    2020 28TH IRANIAN CONFERENCE ON ELECTRICAL ENGINEERING (ICEE), 2020, : 1265 - 1269