Simulation of Off-State degradation at high temperature in High Voltage NMOS transistor with STI architecture

被引:0
|
作者
Bach, Stephane [1 ]
Borella, Fabio [1 ]
Cambieri, Juri [1 ]
Pizzo, Giansalvo [1 ]
Causio, Alessandro [1 ]
Atzeni, Laura [1 ]
Riccardi, Damiano [1 ]
Zullino, Lucia [1 ]
Croce, Giuseppe [1 ]
Nannipieri, Alessandro [2 ]
机构
[1] STMicroelectronics, Technol R&D, Via C Olivetti 2, I-20041 Agrate Brianza, Milano, Italy
[2] Synopsys Switzerland, Zurich, Switzerland
来源
2010 22ND INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD) | 2010年
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中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
After High Temperature Reverse Bias stress, high voltage NMOS transistors designed in 0.18 mu m technologies with STI architecture suffer from R-dson degradation, which can result in long term product failure. In this work, a degradation model is proposed based on results obtained on TCAD simulation, showing very good agreement with the experimental values.
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页码:189 / 192
页数:4
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