Characterization of the HDP-CVD oxide as interlayer dielectric material for sub-quarter micron CMOS

被引：0
|
作者：
Kim, JW [1 ]
Lee, JB [1 ]
Hong, JG [1 ]
Hwang, BK [1 ]
Kim, ST [1 ]
Han, MS [1 ]
机构：
[1] Samsung Elect Co Ltd, Semicond R&D Ctr, Yongin, Kyungki Do, South Korea
来源：
PROCEEDINGS OF THE IEEE 1998 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 1998年
关键词：
D O I：
10.1109/IITC.1998.704921
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The characteristics and process optimization of high density plasma (HDP) CVD oxide as a word line to bitline interlayer dielectric (ILD) material in sub-quarter micron CMOS were investigated. To enhance the gap-filling capability, multi-step deposition of HDP CVD oxide was developed. Self-aligned contact (SAC) scheme could be used with HDP CVD oxide ILD with wide process margin and low thermal budget as compared to conventional methods such as O-3-TEOS undoped silicate glass (USG) and borophosphosilicate glass (BPSG)-reflow. Better or comparable Tr. performance was obtained with HDP CVD oxide compared to BPSG-reflow because of low thermal budget.
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收藏
页码：274 / 276
页数：3
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