共 50 条
- [31] Process integration for through-silicon vias JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A, 2005, 23 (04): : 824 - 829
- [32] Copper-Filled Through-Silicon Vias With Parylene-HT Liner IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2016, 6 (04): : 510 - 517
- [33] Performance Comparison and Analysis by Electrical Measurement for Through-silicon vias (TSV) in Wafer Level Package 2017 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2017,
- [36] A silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnect 58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, : 571 - +
- [37] Circuit Modeling of Shielded Differential Carbon Nanotube Bundle Filled Through-Silicon Vias 2020 IEEE MTT-S INTERNATIONAL CONFERENCE ON NUMERICAL ELECTROMAGNETIC AND MULTIPHYSICS MODELING AND OPTIMIZATION (NEMO 2020), 2020,
- [39] Reliability Evaluation of Copper (Cu) Through-Silicon Vias (TSV) Barrier and Dielectric Liner by Electrical Characterization and Physical Failure Analysis (PFA) 2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017), 2017, : 73 - 79
- [40] Development and Application of a Micro-infrared Photoelasticity System for Stress Evaluation of Through-silicon Vias (TSV) 2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2015, : 1789 - 1794