共 50 条
- [21] Oxide liner, barrier and seed layers, and Cu plating of blind through silicon vias (TSVs) on 300 mm wafers for 3D IC integration Journal of Microelectronics and Electronic Packaging, 2012, 9 (01): : 31 - 36
- [24] Strain Gradient Finite Element Analysis of Size Dependence of Thermal Stresses in Through-Silicon Vias (TSVs) ADVANCES IN MECHANICAL DESIGN, PTS 1 AND 2, 2011, 199-200 : 1920 - +
- [25] Heating Rate Dependence of the Mechanisms of Copper Pumping in Through-Silicon Vias Journal of Electronic Materials, 2019, 48 : 159 - 169
- [29] Development of Cu Seed Layers in Ultra-High Aspect Ratio Through-Silicon-Vias (TSVs) with Small Diameters IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021), 2021, : 1904 - 1909
- [30] Susceptibility Evaluation of 3D Integrated Static Random Access Memory with Through-Silicon Vias (TSVs) 17TH IEEE INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT 2019), 2019,