共 50 条
- [2] Direct Copper Electrodeposition on a Chemical Vapor-Deposited Ruthenium Seed Layer for Through-Silicon Vias 2012 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC), 2012,
- [3] Effect of Microstructure on Via Extrusion Profile and Reliability Implication for Copper Through-Silicon Vias (TSVs) Structures 2014 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE / ADVANCED METALLIZATION CONFERENCE (IITC/AMC), 2014, : 377 - 379
- [4] Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2012, 28 (01): : 53 - 62
- [5] Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits Journal of Electronic Testing, 2012, 28 : 53 - 62
- [8] Pretreatment to assure the copper filling in through-silicon vias Journal of Materials Science: Materials in Electronics, 2016, 27 : 7460 - 7466
- [10] Investigate the Microstructure Changes in Cu Through-Silicon Vias (TSVs) under Thermal Process 2012 13TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2012), 2012, : 397 - 399