Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy

被引：10

作者：

Ejlali, A ^{[1
]}

Schmitz, MT ^{[1
]}

Al-Hashimi, BM ^{[1
]}

Miremadi, SG ^{[1
]}

Rosinger, P ^{[1
]}

机构：

[1] Sharif Univ Technol, Dept Comp Engn, Tehran, Iran

来源：

ISLPED '05: PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2005年

关键词：

dynamic voltage scaling (DVS); single event upset (SEU); information redundancy;

D O I：

10.1109/LPE.2005.195528

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Concerns about the reliability of real-time embedded systems that employ dynamic voltage scaling has recently been highlighted [1,2,3], focusing on transient-fault-tolerance techniques based on time-redundancy. In this paper we analyze the usage of information redundancy in DVS-enabled systems with the aim of improving both the system tolerance to transient faults as well as the energy consumption. We demonstrate through a case study that it is possible to achieve both higher fault-tolerance and less energy using a combination of information and time redundancy when compared with using time redundancy alone. This even holds despite the impact of the information redundancy hardware overhead and its associated switching activities.

引用

页码：281 / 286

页数：6

共 14 条

[1]

[Anonymous], 2004, SYSTEM LEVEL DESIGN

[2] Space, atmospheric, and terrestrial radiation environments [J].

Barth, JL ;

Dyer, CS ;

Stassinopoulos, EG .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2003, 50 (03) :466-482

[3] A dynamic voltage scaled microprocessor system [J].

Burd, TD ;

Pering, TA ;

Stratakos, AJ ;

Brodersen, RW .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (11) :1571-1580

[4]

Johnson B., 1989, Design and Analysis of Fault Tolerant Digital Systems

[5]

Kavi K. M., 1994, Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences. Vol.II: Software Technology (Cat. No.94TH0607-2), P571, DOI 10.1109/HICSS.1994.323226

[6] Tolerance to multiple transient faults for aperiodic tasks in hard real-time systems [J].

Liberato, F ;

Melhem, R ;

Mossé, D .

IEEE TRANSACTIONS ON COMPUTERS, 2000, 49 (09) :906-914

[7] Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits [J].

Maheshwari, A ;

Burleson, W ;

Tessier, R .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (03) :299-311

[8] Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads [J].

Martin, SM ;

Flautner, K ;

Mudge, T ;

Blaauw, D .

IEEE/ACM INTERNATIONAL CONFERENCE ON CAD-02, DIGEST OF TECHNICAL PAPERS, 2002, :721-725

[9] The interplay of power management and fault recovery in real-time systems [J].

Melhem, R ;

Mossé, D ;

Elnozahy, E .

IEEE TRANSACTIONS ON COMPUTERS, 2004, 53 (02) :217-231

[10]

Seifert N, 2001, INT RELIAB PHY SYM, P259, DOI 10.1109/RELPHY.2001.922911

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