共 4 条
[2]
TSV constraints related to temperature excursion, pressure during molding, materials used and handling loads
[J].
MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS,
2009, 15 (01)
:181-190
[3]
Katti G., 2010, INT INT TECHN C IITC, P1, DOI DOI 10.1109/IITC.2010.5510311
[4]
Sloped through wafer vias for 3D wafer level packaging
[J].
57TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2007 PROCEEDINGS,
2007,
:643-+