Interconnect design strategy:: Structures, repeaters and materials toward 0.1μm ULSIs with a giga-hertz clock operation

被引：20

作者：

Takahashi, S ^{[1
]}

Edahiro, M ^{[1
]}

Hayashi, U ^{[1
]}

机构：

[1] NEC Corp Ltd, Silicon Syst Res Labs, Sagamihara, Kanagawa 2291198, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746484

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

With the interconnect analysis using the LSI performance prediction model, the local and global line structures are optimized from 0.18 to 0.1 mu m generations. The chip size enlargement with the wider global line pitch and the inserted repeaters are calculated. It is cleared that both low-rho and low-k; materials are necessary to restrain the chip size enlargement in 0.1 mu m generation.

引用

页码：833 / 836

页数：4