High-Speed Low-Complexity Guided Image Filtering-Based Disparity Estimation

被引:7
作者
Vala, Charan Kumar [1 ]
Immadisetty, Koushik [2 ]
Acharyya, Amit [3 ]
Leech, Charles [4 ]
Balagopal, Vibishna [5 ]
Merrett, Geoff V. [4 ]
Al-Hashimi, Bashir M. [4 ]
机构
[1] Univ Southampton, Southampton SO17 1BJ, Hants, England
[2] Qualcomm Innovat Ctr Inc, Bangalore 560066, Karnataka, India
[3] IIT Hyderabad, Dept Elect Engn, Hyderabad 502285, Andhra Prades, India
[4] Univ Southampton, Sch Elect & Comp Sci, Southampton SO17 IBJ, Hants, England
[5] LumiraDx Technol, London SE1 2AQ, England
基金
英国工程与自然科学研究理事会;
关键词
Guided image filtering; stereo-matching; FPGA; discrete wavelet transform; low-complexity; high-speed; STEREO VISION SYSTEM; VLSI ARCHITECTURE; IMPLEMENTATION; TRANSFORM;
D O I
10.1109/TCSI.2017.2729084
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Stereo vision is a methodology to obtain depth in a scene based on the stereo image pair. In this paper, we introduce a discrete wavelet transform (DWT)-based methodology for a state-of-the-art disparity estimation algorithm that resulted in significant performance improvement in terms of speed and computational complexity. In the initial stage of the proposed algorithm, we apply DWT to the input images, reducing the number of samples to be processed in subsequent stages by 50%, thereby decreasing computational complexity and improving processing speed. Subsequently, the architecture has been designed based on this proposed methodology and prototyped on a Xilinx Virtex-7 FPGA. The performance of the proposed methodology has been evaluated against four standard Middlebury Benchmark image pairs viz. Tsukuba, Venus, Teddy, and Cones. The proposed methodology results in the improvement of about 44.4% cycles per frame, 52% frames/s, and 61.5% and 59.6% LUT and register utilization, respectively, compared with state-of-the-art designs.
引用
收藏
页码:606 / 617
页数:12
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