Optimization of Ti and Co self-aligned silicide RTP for 0.10 μm CMOS

被引：1

作者：

Kittl, JA ^{[1
]}

Hong, QZ ^{[1
]}

Yang, H ^{[1
]}

Yu, N ^{[1
]}

Rodder, M ^{[1
]}

Apte, PP ^{[1
]}

Shiau, WT ^{[1
]}

Chao, CP ^{[1
]}

Breedijk, T ^{[1
]}

Pas, MF ^{[1
]}

机构：

[1] Texas Instruments Inc, Silicon Technol Dev, Dallas, TX 75243 USA

来源：

ADVANCED INTERCONNECTS AND CONTACT MATERIALS AND PROCESSES FOR FUTURE INTEGRATED CIRCUITS | 1998年 / 514卷

关键词：

D O I：

10.1557/PROC-514-255

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

As CMOS technologies are scaled to 0.10 mu m and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 mu m CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 mu m gates.

引用

页码：255 / 260

页数：6

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