Ultra Low-Cost Through-Silicon Holes (TSHs) Interposers for 3D IC Integration SiPs

被引：0
|
作者：
Wu, Sheng-Tsai [1 ]
Lau, John H. [1 ]
Chien, Heng-Chieh [1 ]
Hung, Jui-Feng [1 ]
Dai, Ming-Ji [1 ]
Chao, Yu-Lin [1 ]
Tain, Ra-Min [1 ]
Lo, Wei-Chung [1 ]
Kao, Ming-Jer [1 ]
机构：
[1] ITRI, Elect & Optoelect Res Lab, Hsinchu 310, Taiwan
来源：
2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2012年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this study, a very low-cost silicon interposer with many through-silicon holes (TSHs) for 3D IC integration system-in-package (SiP) applications is proposed. Unlike TSVs (through-silicon vias), the uniqueness of this design is there is not the dielectric layer, barrier layer, seed layer, filled Cu, and thus CMP and TSV Cu reveal are not necessary for the TSHs. The vertical interconnects between (face-to-face) the top chips and bottom chips of the TSH interposer are through Cu wires or columns. The electrical, thermal and mechanical behaviors of this new design are demonstrated by nonlinear finite element simulations.
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页码：1618 / 1624
页数：7
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