Memory bank predictors

被引：2

作者：

Bieschewski, S ^{[1
]}

Parcerisa, JM ^{[1
]}

González, A ^{[1
]}

机构：

[1] Univ Politecn Catalunya, Dept Arquitectura Comp, Barcelona, Spain

来源：

2005 IEEE International Conference on Computer Design: VLSI in Computers & Processors, Proceedings | 2005年

关键词：

memory bank prediction; clustered; microarchitectures;

D O I：

10.1109/ICCD.2005.73

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access can help to improve the performance in several ways. One scenario that is likely to become increasingly important is clustered microprocessors with a distributed cache. This work presents a study of different cache bank predictors. We show that effective bank predictors can be implemented with relatively low cost. For instance, a predictor of approximately 4 Kbytes is shown to achieve an average hit rate of 78% for SPECint2000 when used to predict accesses to an 8-bank cache memory in a contemporary superscalar processor. We also show how a predictor can be used to reduce the communication latency caused by memory accesses in a clustered microarchitecture with a distributed cache design.

引用

页码：666 / 668

页数：3