Power Dissipation Effects on 28nm FPGA-Based System on Chips Neutron Sensitivity

被引:0
|
作者
Bruni, G. [1 ]
Rech, P. [2 ]
Tambara, L. [2 ]
Nazar, G. L. [2 ]
Kastensmidt, F. L. [2 ]
Reis, R. [2 ]
Paccagnella, A. [1 ]
机构
[1] Padova Univ, Dipartimento Eletron & Infonnat, DEI, Padua, Italy
[2] Univ Fed Rio Grande Do Sul, Inst Infonnat, Porto Alegre, RS, Brazil
来源
2014 22ND INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC) | 2014年
关键词
FPGA; Power Dissipation; Radiation Sensitivity; Temperature; System On Chips; INDUCED SOFT ERRORS; SRAM;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Modern System on Chips (SoCs) and embedded electronic devices work at very high frequencies, which have the countermeasure of increasing the power dissipation and, consequently, the silicon die temperature. The presented radiation experiments on a 28nm FPGA-based SoC demonstrate that the temperature variation caused by a higher operating frequency affects the FPGA configuration memory cross section. An evaluation and discussion of the observed reliability dependence on power dissipation effects on practical application is also presented.
引用
收藏
页数:6
相关论文
共 50 条
  • [1] SSTL Based Power Efficient Implementation of DES Security Algorithm on 28nm FPGA
    Pandey, Bishwajeet
    Thind, Vandana
    Sandhu, Simran Kaur
    Walia, Tamanna
    Sharma, Sumit
    INTERNATIONAL JOURNAL OF SECURITY AND ITS APPLICATIONS, 2015, 9 (07): : 267 - 273
  • [2] SSTL Based Thermal and Power Efficient RAM Design on 28nm FPGA for Spacecraft
    Kalia, Kartik
    Pandey, Bishwajeet
    Hussain, D. M. A.
    2016 INTERNATIONAL CONFERENCE ON SMART GRID AND CLEAN ENERGY TECHNOLOGIES (ICSGCE), 2016, : 313 - 317
  • [3] Low power squarer design using Ekadhikena Purvena on 28nm FPGA
    Jaypee Institute of Information Technology, Noida, India
    不详
    Int. J. Control Autom., 5 (281-288):
  • [4] Capacitance Scaling Aware Power Optimized Register Design And Implementation on 28nm FPGA
    Banshal, Sumit Kumar
    Pandey, Bishwajeet
    Brenda, S. J.
    2014 INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATION AND INFORMATICS (ICCCI), 2014,
  • [5] IO Standard Based Energy Efficient ALU Design and Implementation on 28nm FPGA
    Pandey, Bishwajeet
    Yadav, Jyotsana
    Pattanaik, Manisha
    2013 ANNUAL IEEE INDIA CONFERENCE (INDICON), 2013,
  • [6] LVCMOS based energy efficient sindhi unicode reader for natural processing on 28nm FPGA
    Madhok, Shivani
    Kaur, Inderpreet
    Taxali, Vanshaj
    Thind, Vandana
    Dabas, Sweety
    Madhok, Tushar
    International Journal of u- and e- Service, Science and Technology, 2015, 8 (08) : 207 - 214
  • [7] HSTL IO standard based energy efficient FIR filter design on 28nm FPGA
    Madhok, Shivani
    Singh, Navdeep
    Kaur, Jasleen
    Nanda, Khyati
    Dabas, Sweety
    Dhankar, Minal
    International Journal of Control and Automation, 2015, 8 (07): : 47 - 54
  • [8] SSTL IO standard based energy efficient digital clock design on 28nm FPGA
    Madhok, Shivani
    Singh, Navdeep
    Fazili, Furqan
    Nagah, Sumita
    Kaur, Ravinder
    Dabas, Sweety
    International Journal of Control and Automation, 2015, 8 (06): : 35 - 42
  • [9] Designing of Power Efficient ROM Using LVTTL and Mobile-DDR IO Standard on 28nm FPGA
    Agrawal, Tarun
    Srivastava, Vivek
    Kumar, Anjan
    2015 INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND COMMUNICATION NETWORKS (CICN), 2015, : 1334 - 1337
  • [10] Physical Implementation of Low Power SoC Chip based on SEC 28nm FDS
    Zhu, Jiong
    Jin, Shirley
    Chen, Jun
    2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2017,