共 50 条
- [1] SSTL Based Power Efficient Implementation of DES Security Algorithm on 28nm FPGA INTERNATIONAL JOURNAL OF SECURITY AND ITS APPLICATIONS, 2015, 9 (07): : 267 - 273
- [2] SSTL Based Thermal and Power Efficient RAM Design on 28nm FPGA for Spacecraft 2016 INTERNATIONAL CONFERENCE ON SMART GRID AND CLEAN ENERGY TECHNOLOGIES (ICSGCE), 2016, : 313 - 317
- [3] Low power squarer design using Ekadhikena Purvena on 28nm FPGA Int. J. Control Autom., 5 (281-288):
- [4] Capacitance Scaling Aware Power Optimized Register Design And Implementation on 28nm FPGA 2014 INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATION AND INFORMATICS (ICCCI), 2014,
- [5] IO Standard Based Energy Efficient ALU Design and Implementation on 28nm FPGA 2013 ANNUAL IEEE INDIA CONFERENCE (INDICON), 2013,
- [7] HSTL IO standard based energy efficient FIR filter design on 28nm FPGA International Journal of Control and Automation, 2015, 8 (07): : 47 - 54
- [8] SSTL IO standard based energy efficient digital clock design on 28nm FPGA International Journal of Control and Automation, 2015, 8 (06): : 35 - 42
- [9] Designing of Power Efficient ROM Using LVTTL and Mobile-DDR IO Standard on 28nm FPGA 2015 INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND COMMUNICATION NETWORKS (CICN), 2015, : 1334 - 1337
- [10] Physical Implementation of Low Power SoC Chip based on SEC 28nm FDS 2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2017,