Array transistor design challenges in trench capacitor DRAM technology

被引：0

作者：

Li, YJ ^{[1
]}

Sim, J ^{[1
]}

Mandelman, J ^{[1
]}

McStay, K ^{[1
]}

Ye, QY ^{[1
]}

Bronner, G ^{[1
]}

机构：

[1] IBM Corp, Hopewell Jct, NY 12533 USA

来源：

2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS | 2001年

关键词：

D O I：

10.1109/VTSA.2001.934489

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

BuriEd Strap Trench (BEST) array cell design has been extended for more than 4 generations. However, significant scaling challenges in planar trench DRAM technology will be encountered below the 0.1 mum generation. In this paper. we review the key factors that limit the scaling of the BEST array cell, further analyze the scaling challenges considering design for manufacturability, and finally discuss other design and/or technology innovations including the vertical array transistor to overcome scaling limitations.

引用

页码：85 / 88

页数：4

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