A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs

被引:0
作者
Gaillardon, Pierre-Emmanuel [1 ]
Tang, Xifan [1 ]
Sandrini, Jury [1 ]
Thammasack, Maxime [1 ]
Omam, Somayyeh Rahimian [1 ]
Sacchetto, Davide [1 ]
Leblebici, Yusuf [1 ]
De Micheli, Giovanni [1 ]
机构
[1] Swiss Fed Inst Technol, Lausanne, Switzerland
来源
2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) | 2015年
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Field Programmable Gate Arrays (FPGAs) rely heavily on complex routing architectures. The routing structures use programmable switches and account for a significant share in the total area, delay and power consumption numbers. With the ability of being monolithically integrated with CMOS chips, Resistive Random Access Memories (RRAMs) enable high-performance routing architectures through the replacement of Static Random Access Memory (SRAM)-based programming switches. Exploiting the very low on-resistance state achievable by RRAMs as well as the improved tolerance to power supply reduction, RRAM-based routing multiplexers can be used to significantly reduce the power consumption of FPGA systems with no performance compromises. By evaluating the opportunities of ultra-low-power RRAM-based FPGAs at the system level, we see an improvement of 12%, 26% and 81% in area, delay and power consumption at a mature technology node.
引用
收藏
页码:1203 / 1208
页数:6
相关论文
共 17 条
  • [1] Flexible Circuits and Architectures for Ultralow Power
    Calhoun, Benton Highsmith
    Ryan, Joseph F.
    Khanna, Sudhanshu
    Putic, Mateja
    Lach, John
    [J]. PROCEEDINGS OF THE IEEE, 2010, 98 (02) : 267 - 282
  • [2] Chen Y., 2012, FPL
  • [3] Cheng L., 2005, IEEE TCAD
  • [4] Cheng L., 2005, DAC
  • [5] FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects
    Cong, Jason
    Xiao, Bingjun
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2014, 22 (04) : 864 - 877
  • [6] Gaillardon P.-E., 2012, IEEE IFIP VLSI SOC
  • [7] Gaillardon P.-E., 2010, ICECS
  • [8] Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs
    Gaillardon, Pierre-Emmanuel
    Sacchetto, Davide
    Beneventi, Giovanni Betti
    Ben Jamaa, M. Haykel
    Perniola, Luca
    Clermidy, Fabien
    O'Connor, Ian
    De Micheli, Giovanni
    [J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2013, 12 (01) : 40 - 50
  • [9] Kazi I., 2014, ENERGY RELIABILITY T, V61, P3155
  • [10] Kuon I, 2009, QUANTIFYING AND EXPLORING THE GAP BETWEEN FPGAS AND ASICS, P1