Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks

被引:147
作者
Zhan, Chen [1 ,2 ,3 ]
Fang, Zhenman [2 ]
Zhou, Peipei [2 ]
Pan, Peichen [3 ]
Cong, Jason [1 ,2 ,3 ]
机构
[1] Peking Univ, Ctr Energy Efficient Comp & Applicat, Beijing, Peoples R China
[2] Univ Calif Los Angeles, Dept Comp Sci, Los Angeles, CA 90095 USA
[3] Falcon Comp Inc, Los Angeles, CA USA
来源
2016 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) | 2016年
关键词
COPROCESSOR;
D O I
10.1145/2966986.2967011
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
With the recent advancement of multilayer convolutional neural networks (CNN), deep learning has achieved amazing success in many areas, especially in visual content understanding and classification. To improve the performance and energy-efficiency of the computation-demanding CNN, the FPGA-based acceleration emerges as one of the most attractive alternatives. In this paper we design and implement Caffeine, a hardware/software co-designed library to efficiently accelerate the entire CNN on FPGAs. First, we propose a uniformed convolutional matrix-multiplication representation for both computation-intensive convolutional layers and communication-intensive fully connected (FCN) layers. Second, we design Caffeine with the goal to maximize the underlying FPGA computing and bandwidth resource utilization, with a key focus on the bandwidth optimization by the memory access reorganization not studied in prior work. Moreover, we implement Caffeine in the portable high-level synthesis and provide various hardware/software definable parameters for user configurations. Finally, we also integrate Caffeine into the industry-standard software deep learning framework Caffe. We evaluate Caffeine and its integration with Caffe by implementing VGG16 and AlexNet network on multiple FPGA platforms. Caffeine achieves a peak performance of 365 GOPS on Xilinx KU060 FPGA and 636 GOPS on Virtex7 690t FPGA. This is the best published result to our best knowledge. We achieve more than 100x speedup on FCN layers over previous FPGA accelerators. An end-to-end evaluation with Caffe integration shows up to 7.3x and 43.5x performance and energy gains over Caffe on a 12-core Xeon server, and 1.5x better energy-efficiency over the GPU implementation on a medium-sized FPGA (KU060). Performance projections to a system with a high-end FPGA (Virtex7 690t) shows even higher gains.
引用
收藏
页数:8
相关论文
共 30 条
[21]   A Massively Parallel Coprocessor for Convolutional Neural Networks [J].
Sankaradas, Murugan ;
Jakkula, Venkata ;
Cadambi, Srihari ;
Chakradhar, Srimat ;
Durdanovic, Igor ;
Cosatto, Eric ;
Graf, Hans Peter .
2009 20TH IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, 2009, :53-60
[22]  
Simonyan K, 2015, Arxiv, DOI arXiv:1409.1556
[23]   Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks [J].
Suda, Naveen ;
Chandra, Vikas ;
Dasika, Ganesh ;
Mohanty, Abinash ;
Ma, Yufei ;
Vrudhula, Sarma ;
Seo, Jae-Sun ;
Cao, Yu .
PROCEEDINGS OF THE 2016 ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS (FPGA'16), 2016, :16-25
[24]  
Szegedy C, 2015, PROC CVPR IEEE, P1, DOI 10.1109/CVPR.2015.7298594
[25]   DeepFace: Closing the Gap to Human-Level Performance in Face Verification [J].
Taigman, Yaniv ;
Yang, Ming ;
Ranzato, Marc'Aurelio ;
Wolf, Lior .
2014 IEEE CONFERENCE ON COMPUTER VISION AND PATTERN RECOGNITION (CVPR), 2014, :1701-1708
[26]   Roofline: An Insightful Visual Performance Model for Multicore Architectures [J].
Williams, Samuel ;
Waterman, Andrew ;
Patterson, David .
COMMUNICATIONS OF THE ACM, 2009, 52 (04) :65-76
[27]   Large-scale Deep Learning at Baidu [J].
Yu, Kai .
PROCEEDINGS OF THE 22ND ACM INTERNATIONAL CONFERENCE ON INFORMATION & KNOWLEDGE MANAGEMENT (CIKM'13), 2013, :2211-2211
[28]   Visualizing and Understanding Convolutional Networks [J].
Zeiler, Matthew D. ;
Fergus, Rob .
COMPUTER VISION - ECCV 2014, PT I, 2014, 8689 :818-833
[29]  
Zhang C, 2015, P 2015 ACM SIGDA INT, P161, DOI 10.1145/2684746.2689060
[30]  
Zuo W., 2013, Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, P9