A fully integrated 24 GHZ fractional PLL with a low-power synchronized ring oscillator divider

被引：1

作者：

Mazouffre, O ^{[1
]}

Lapuyade, H ^{[1
]}

Begueret, JB ^{[1
]}

Cathelin, A ^{[1
]}

Belot, D ^{[1
]}

Deval, Y ^{[1
]}

Hellmuth, P ^{[1
]}

机构：

[1] Univ Bordeaux 1, IXL Lab, F-33405 Talence, France

来源：

PROCEEDINGS OF THE 2005 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING | 2005年

关键词：

PLL; prescaler; divider; low-power; 24; GHz; BiCMOS SiGe technology;

D O I：

10.1109/BIPOL.2005.1555189

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design and the experimental measurements of a 24 GHz fully integrated fractional PLL with a new low power prescaler. This circuit is implemented in a 0.25 mu m SiGe:C process from STMicroelectronics (BiCMOS7R.F). The PLL power dissipation is 148 mW and fulfills a 24.8 to 26.8 GHz frequency locking range, while exhibiting a phase noise of -97 dBc/Hz at 100 KHz from the carrier. The simulated PLL unity-gain bandwidth is 27 MHz, with a phase margin of 56 degrees. The PLL uses a new latch-based prescaler (SRO) which exhibits a very low power dissipation of 0.74 GHz/mW.

引用

页码：6 / 9

页数：4