VLSI implementation of a high-performance 32-bit RISC microprocessor

被引：0

作者：

Li, X ^{[1
]}

Ji, LW ^{[1
]}

Shen, B ^{[1
]}

Li, WH ^{[1
]}

Zhang, QL ^{[1
]}

机构：

[1] Fudan Univ, ASIC, Shanghai 200433, Peoples R China

来源：

2002 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS AND WEST SINO EXPOSITION PROCEEDINGS, VOLS 1-4 | 2002年

关键词：

RISC microprocessor; VLSI; pipeline; CPI; MIPS;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The microprocessor is one of the most important blocks of the SoC. Considering high-performance, we implement a 32-bit RISC microprocessor, named as FDU32, with instruction sets compatible with ARM7TDMI. By using 5-stage pipeline and improving the circuit structure, FDU32 obtains 67% increment in max clock rate, 11% reduction in CPI and 86% increment in MIPS compared with ARM7TDMI at the same 0.35 mum CMOS process, and only the transistor count increases a little. FDU32 has passed the FPGA verification and taped out.

引用

页码：1458 / 1461

页数：4