VLSI implementation of a high-performance 32-bit RISC microprocessor

被引：0

作者：

Li, X ^{[1
]}

Ji, LW ^{[1
]}

Shen, B ^{[1
]}

Li, WH ^{[1
]}

Zhang, QL ^{[1
]}

机构：

[1] Fudan Univ, ASIC, Shanghai 200433, Peoples R China

来源：

2002 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS AND WEST SINO EXPOSITION PROCEEDINGS, VOLS 1-4 | 2002年

关键词：

RISC microprocessor; VLSI; pipeline; CPI; MIPS;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The microprocessor is one of the most important blocks of the SoC. Considering high-performance, we implement a 32-bit RISC microprocessor, named as FDU32, with instruction sets compatible with ARM7TDMI. By using 5-stage pipeline and improving the circuit structure, FDU32 obtains 67% increment in max clock rate, 11% reduction in CPI and 86% increment in MIPS compared with ARM7TDMI at the same 0.35 mum CMOS process, and only the transistor count increases a little. FDU32 has passed the FPGA verification and taped out.

引用

页码：1458 / 1461

页数：4

共 41 条

[1] A NOVEL 32-BIT RISC MICROPROCESSOR FOR EMBEDDED SYSTEMS
MULLER, O
IEICE TRANSACTIONS ON ELECTRONICS, 1992, E75C (10) : 1196 - 1201
[2] AN 18-MHZ, 32-BIT VLSI MICROPROCESSOR
BURKHART, KP
FORSYTH, MA
HAMMER, ME
TANKSALVALA, DF
HEWLETT-PACKARD JOURNAL, 1983, 34 (08): : 7 - &
[3] An Asynchronous Implementation of a 32-bit DLX Microprocessor
Dumaguing, Christian Loyd G.
Khan, Amos Kaiser K.
Parungao, Mark Anthony D.
Alvarez, Anastacia B.
Reyes, Joy Alinda P.
2009 INTERNATIONAL CONFERENCE ON INFORMATION AND MULTIMEDIA TECHNOLOGY, PROCEEDINGS, 2009, : 503 - 506
[4] 32-bit RISC CPU Based on MIPS
Yi, Kui
Ding, Yue-Hua
PROCEEDINGS OF THE 2009 SECOND PACIFIC-ASIA CONFERENCE ON WEB MINING AND WEB-BASED APPLICATION, 2009, : 124 - 128
[5] Implementation of a 32-bit MIPS Based RISC Processor using Cadence
Topiwala, Mohit N.
Saraswathi, N.
2014 INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES (ICACCCT), 2014, : 979 - 983
[6] Design and Implementation of 32-bit MIPS-Based RISC Processor
Patra, Sumit
Kumar, Sunil
Verma, Swati
Kumar, Arvind
ADVANCES IN VLSI, COMMUNICATION, AND SIGNAL PROCESSING, 2020, 587 : 747 - 757
[7] Design and Implementation of 32-bit Functional Unit for RISC architecture applications
Samanth, Rashmi
Amin, Ashwini
Nayak, Subramanya G.
2020 5TH INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICDCS' 20), 2020, : 46 - 48
[8] A 0.9-V CMOS 32-BIT MICROPROCESSOR
HARIGAI, H
SUZUKI, H
SAKAI, T
YANO, Y
NEC RESEARCH & DEVELOPMENT, 1995, 36 (01): : 42 - 51
[9] 32-bit RISC CPU Based on MIPS Instruction Fetch Module Design
Yi, Kui
Ding, Yue-Hua
FIRST IITA INTERNATIONAL JOINT CONFERENCE ON ARTIFICIAL INTELLIGENCE, PROCEEDINGS, 2009, : 754 - 760
[10] Instruction Fetch Module Design of 32-bit RISC CPU Based on MIPS
Ding, Yuehua
Yi, Kui
Sun, Ping
DCABES 2008 PROCEEDINGS, VOLS I AND II, 2008, : 1109 - 1116

← 1 2 3 4 5 →