Design and Implementation of a Reversible Central Processing Unit

This work addresses the reversible circuit design using novel modularization approach by presenting architecture of a logically reversible processor based on the Von Neumann architecture that can operate with very low power consumption, protection of power analysis attack and long span of life due to less heat dissipation. The organization and architecture of the proposed processor is designed from scratch. Sequential algorithms are proposed to produce the components of the reversible processor. The capabilities of the new processor is determined, the datapath layout is designed to handle the necessary capabilities, the instruction format is defined and the necessary logic is also constructed to control the datapath. To estimate the execution time of the algorithm, we consider the computational complexity, memory access patterns and the complexity of the instructions. Existing component designs are compared with the proposed components and theorems and lemmas are presented to prove the superiority of the proposed architecture. The proposed design is simulated and the simulation result verifies the correctness of the proposed design.