Low-latency decoding of EG LDPC codes

被引:7
|
作者
Zhang, Juntan
Yedidia, Jonathan S.
Fossorier, Marc P. C.
机构
[1] Univ Hawaii, Dept Elect Engn, Honolulu, HI 96822 USA
[2] Mitsubishi Elect Res Labs, Cambridge, MA 02139 USA
关键词
bit-flipping (BF) decoding; low-density parity-check (LDPC) codes; optical communications; weighted BF decoding;
D O I
10.1109/JLT.2007.903311
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We describe simple iterative decoders for low-density parity-check codes based on Euclidean geometries, suitable for practical very-large-scale-integration implementation in applications requiring very fast decoders. The decoders are based on shuffled and replica -shuffled versions of iterative bit-flipping (BF) and quantized weighted BF schemes. The proposed decoders converge faster and provide better ultimate performance than standard BF decoders. We present simulations that illustrate the performance versus complexity trade offs for these decoders. We can show in some cases through importance sampling that no significant error floor exists.
引用
收藏
页码:2879 / 2886
页数:8
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