Consideration of UFET Architecture for the 5 nm Node and beyond Logic Transistor

In this paper, we propose a trench MOS architecture for the upcoming 5 nm node and beyond logic transistor. The intended device has a gate formed vertically downward, with added spacers along the gate to S/D sidewall. In doing so, the recessed device having longer channel length (than the defined gate footprint) would be a constructive approach to limit the short channel effects (SCE). The novel transistor has the potential to enable the scaling of gate length (footprint) less than 10 nm and contacted gate pitch below 32 nm, resulting in the smallest active area (on-wafer footprint) for a single device. Novel process steps are simulated depicting easier fabrication while the electrical analysis shows a better electrostatic control over any unwanted leakage flows. Along with the area scaling and SCE control, the planar upper surface allows a vertical integration. Growing another flipped device on top surface permits the designer to implement a logic circuit on a footprint of a single device, achieving similar to 50% area gain further. TCAD based simulations were performed to design and characterize the performances of an individual device and the vertical inverter.