A Non-Redundant Low-Power Flip Flop with Stacked Transistors in a 65 nm Thin BOX FDSOI Process

We propose a non-redundant Flip-Flop (FF) with stacked transistors based on Adaptive Coupling Flip-Flop (ACFF) with lower power consumption in a 65 nm Fully Depleted Silicon On Insulator (FDSOI) process. The slave latch in ACFF is much weaker against soft errors than the master latch. We design several FFs with stacked transistors in the master or slave latches. We investigate radiation hardness of the proposed FFs by alpha particle and neutron irradiation test. The proposed FFs have higher radiation hardness than conventional DFF. There is no error in the proposed AC slave stacked FF which has stacked transistors only in the slave latch by alpha particle and neutron irradiation test. It can decrease soft error rates despite the performance equivalent to that of ACFF.