Analysis of electromagnetic coupling and current distribution inside a power module

被引：28

作者：

Martin, Christian ^{[1
]}

Schanen, Jean-Luc

Guichon, Jean-Michel

Pasterczyk, Robert

机构：

[1] UJF, INPG, CNRS,UMR 5529, French Natl Ctr Sci Res,Electrotech Lab Grenoble, F-38402 St Martin Dheres, France

[2] Merlin Gerin MGE UPS Syst, F-38334 Saint Ismier, France

来源：

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS | 2007年 / 43卷 / 04期

关键词：

Layout optimization; Paralleling devices; Partial element equivalent circuit (PEEC) method; Power drive interaction; Power electronics; Power modules;

D O I：

10.1109/TIA.2007.900453

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Due to high-current commutation speed, it has become necessary to minimize stray inductances to reduce over-voltage. This is a great challenge for the power-converter designer. Integration of converters into ever smaller packages decreases stray inductance considerably but, at the same time, increases other phenomena (thermal issues and electromagnetic-compatibility disturbances) capable of decreasing reliability and efficiency of the system. This paper presents a generic equivalent cabling model and examines the impact of parasitic inductance on current-distribution imbalance. This paper could, therefore, be used in thermal analysis in order to better understand the influence of packaging.

引用

页码：893 / 901

页数：9

共 13 条

[1]

AKHBARI M, 1998, C REC 33 IEEE IAS AN, V2, P1078

[2]

Chen JZ, 2001, APPL POWER ELECT CO, P1002, DOI 10.1109/APEC.2001.912489

[3]

CONSOLI A, 1999, P COPEB FOZ DO IG BR

[4]

HE J, 1999, C REC 34 IEEE IAS AN, V2, P1440

[5] 3-DIMENSIONAL INTERCONNECT ANALYSIS USING PARTIAL ELEMENT EQUIVALENT-CIRCUITS [J].

HEEB, H ;

RUEHLI, AE .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 1992, 39 (11) :974-982

[6] AN EXPERIMENTALLY VERIFIED IGBT MODEL IMPLEMENTED IN THE SABER CIRCUIT SIMULATOR [J].

HEFNER, AR ;

DIEBOLT, DM .

IEEE TRANSACTIONS ON POWER ELECTRONICS, 1994, 9 (05) :532-542

[7] Original cabling conditions to insure balanced current during switching transitions between paralleled semiconductors [J].

Jeannin, PO ;

Schanen, JL ;

Clavel, E .

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 2002, 38 (01) :181-188

[8]

MARTIN C, 2003, P EPE TOUL FRANC SEP

[9] STATE-VARIABLE MODELING OF THE POWER PIN DIODE USING AN EXPLICIT APPROXIMATION OF SEMICONDUCTOR-DEVICE EQUATIONS - A NOVEL-APPROACH [J].

MOREL, H ;

GAMAL, SH ;

CHANTE, JP .

IEEE TRANSACTIONS ON POWER ELECTRONICS, 1994, 9 (01) :112-120

[10] Impedance criterion for power modules comparison [J].

Schanen, JL ;

Martin, C ;

Frey, D ;

Pasterczyk, RJ .

IEEE TRANSACTIONS ON POWER ELECTRONICS, 2006, 21 (01) :18-26

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