A 27-41 GHz Frequency Doubler With Conversion Gain of 12 dB and PAE of 16.9%

被引：27

作者：

Li, Jiankang ^{[1
,2
]}

Xiong, Yong-Zhong ^{[3
]}

Goh, Wang Ling ^{[4
]}

Wu, Wen ^{[1
]}

机构：

[1] Nanjing Univ Sci & Technol, Ministerial Key Lab JGMT, Sch Elect & Opt Engn, Nanjing 210094, Jiangsu, Peoples R China

[2] MicroArray Technol, Chengdu 611731, Peoples R China

[3] Inst Microelect Singapore, Singapore 117685, Singapore

[4] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore

来源：

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2012年 / 22卷 / 08期

关键词：

Balanced frequency doubler; high efficiency; high output power; SiGe BiCMOS; BAND;

D O I：

10.1109/LMWC.2012.2205228

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 27-41 GHz monolithic balanced frequency doubler fabricated using the 0.13 mu m SiGe BiCMOS technology is presented in this letter. The balanced doubler consists of a balun, a driver amplifier (DA), a common-base (CB) doubling core and a medium power amplifier. The CB topology is used to increase the bandwidth and for the ease of matching with the balun. The proposed frequency doubler attained a measured gain of 16.8-19.8 dB, an output power of 1.3-4.3 dBm, and a fundamental rejection of better than 25.7 dB (from 27 to 41 GHz) at an input power of -15.5 dBm. An maximum output power of 8 dBm with dc power consumption of 35 mW and corresponding power added efficiency (PAE) of 16.9% have also been achieved. The chip size is 0.75 mm x 0.45 mm.

引用

页码：427 / 429

页数：3

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