Network Interface to Synchronize Multiple Packets on NoC-based Systems-on-Chip

The cores of a System-on-Chip (SoC) connected by Networks-on-Chip (NoCs) need interfaces to properly send and receive packets. However, in this interfacing, different situations can occur when heterogeneous cores are applied. Applications may require, for example, an irregular traffic behavior or present a large bandwidth variation. These situations may lead to problems in data synchronization. In this paper we show a simple and efficient synchronization solution, which although known in the literature, has not yet been applied to NoC-based systems scenario. Using a network interface as the synchronization mechanism, the proposed circuit handles data dependencies instead of letting each core solve the synchronization problems at higher levels. As case study, an H.264 video decoder was used to show the need and advantage of our approach. The proposed design is FIFO-based and can be applied when multiple packets from different sources need to be synchronized in a single destination. Simulations were performed to verify the functionality and efficiency of the synchronization solution. These interfaces were implemented in VHDL and synthesized using an 180nm CMOS technology.