Low power double edge-triggered flip-flop using one latch

被引：11

作者：

Strollo, AGM ^{[1
]}

Napoli, E ^{[1
]}

Cimino, C ^{[1
]}

机构：

[1] Univ Naples, I-80125 Naples, Italy

来源：

ELECTRONICS LETTERS | 1999年 / 35卷 / 03期

关键词：

D O I：

10.1049/el:19990164

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low power double edge-triggered (DET) flip-flop using a single latch is presented. In the proposed circuit, data are sampled into the latch juring a short transparency period for each edge of the clock signal. The proposed flip-flop requires small silicon area and has lower power dissipation with respect to previously reported DET flip-flops.

引用

页码：187 / 188

页数：2

共 5 条

[1] Low-power double-edge triggered flipflop [J].