Assertion-based verification: Industry myths to realities

被引:0
作者
Foster, Harry [1 ]
机构
[1] Mentor Graph Corp, Plano, TX USA
来源
COMPUTER AIDED VERIFICATION | 2008年 / 5123卷
关键词
assertion; assertion-based verification; debugging; formal verification; functional verification; property specification simulation;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Debugging, on average, has grown to consume more than 60% of today's ASIC and SoC verification effort. Clearly, this is a topic the industry must address, and some organizations have done just that. Those that have adopted an assertion-based verification (ABV) methodology have seen significant reduction in simulation debugging time (as much as 50% [1]) due to improved observability. Furthermore, organizations that have embraced an ABV methodology are able to take advantage of more advanced verification techniques, such as formal verification, thus improving their overall verification quality and results. Nonetheless, even with multiple published industry case studies from various early adopters-each touting the benefits of applying ABV-the industry as a whole has resisted adopting assertion-based techniques. This tutorial provides an industry survey of today's ABV landscape, ranging from myths to realities. Emerging challenges and possible research opportunities are discussed. The following extended abstract provides a reference on which the tutorial builds.
引用
收藏
页码:5 / 10
页数:6
相关论文
共 50 条
[41]   Generation and Verification of Executable Assurance Case by Model-based Engineering [J].
Yan, Fang .
2021 IEEE INTERNATIONAL SYMPOSIUM ON SOFTWARE RELIABILITY ENGINEERING WORKSHOPS (ISSREW 2021), 2021, :323-326
[42]   ASIC Verification: Integrating Formal Verification With HDL-Based Courses [J].
Massoumi, Mehran ;
Sagahyroon, Assim .
COMPUTER APPLICATIONS IN ENGINEERING EDUCATION, 2010, 18 (02) :269-276
[43]   Verification of a Radio-Based Signaling System Using the STATEMATE Verification Environment [J].
Werner Damm ;
Jochen Klose .
Formal Methods in System Design, 2001, 19 :121-141
[44]   JumpSAT Based System Verification Scenarios [J].
Pulka, Andrzej .
2018 INTERNATIONAL CONFERENCE ON SIGNALS AND ELECTRONIC SYSTEMS (ICSES 2018), 2018, :301-306
[45]   Verification of a radio-based signaling system using the STATEMATE verification environment [J].
Damm, W ;
Klose, J .
FORMAL METHODS IN SYSTEM DESIGN, 2001, 19 (02) :121-141
[46]   Verification Approach Based on Emulation Technology [J].
Koczor, Arkadiusz ;
Matoga, Lukasz ;
Penkala, Piotr ;
Pawlak, Adam .
2016 IEEE 19TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2016, :169-174
[47]   Software verification based on linear programming [J].
Dellacherie, S ;
Devulder, S ;
Lambert, JL .
FM'99-FORMAL METHODS, VOL II, 1999, 1709 :1147-1165
[48]   Verifying Cross-Layer Interactions Through Formal Model-Based Assertion Generation [J].
Salehi Fathabadi, Asieh ;
Dalvandi, Mohammadsadegh ;
Butler, Michael ;
Al-Hashimi, Bashir M. .
IEEE EMBEDDED SYSTEMS LETTERS, 2020, 12 (03) :83-86
[49]   Formal Verification of a Fuzzy Rule-Based Classifier Using the Prototype Verification System [J].
Gebreyohannes, Solomon ;
Karimoddini, Ali ;
Homaifar, Abdollah ;
Esterline, Albert .
FUZZY INFORMATION PROCESSING, NAFIPS 2018, 2018, 831 :1-12
[50]   Verification of Embedded Systems Based on Interval Analysis [J].
Iñigo Ugarte ;
Pablo Sanchez .
International Journal of Parallel Programming, 2005, 33 :697-720