Development of electron-beam lithography for power semiconductor devices

The power semiconductor device making by employment of electron-beam lithography is considered. The ZBA-21 tool with modified data system was applied for lithography. Our exposure strategy was developed for increase of writing speed. The analytical solution for the optimum beam size was obtained, and the lower limit of maximum beam size has been calculated for layouts of power semiconductor devices. A new translation program dividing layout on standard figures was used. At the output this program gives the rectangles having widths with divisible sizes. The maximum beam size is chosen as greater common divisor of these sizes. This strategy permits to use the beam current more effective, to decrease waste time on dynamic focusing, and to smooth the temperature field. The making of static induction thyristor by employment of electron-beam lithography is cited as an example. The reproducibility of element's sizes on wafer has been investigated.