Fault Collapsing with Linear Complexity in Digital Circuits

被引：0

作者：

Ubar, R. ^{[1
]}

Mironov, D. ^{[1
]}

Raik, J. ^{[1
]}

Jutman, A. ^{[1
]}

机构：

[1] TTU, Dept Comp Engn, EE-19086 Tallinn, Estonia

来源：

2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS | 2010年

关键词：

combinational circuits; test generation; fault collapsing; fault equivalence and dominance; BDDs; IDENTIFICATION; EQUIVALENCE; GRAPH;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The paper presents a new structural fault-independent fault collapsing method for test generation based on the topology analysis of the circuit, which has linear complexity. Fault collapsing is carried out by superposition of binary decision diagrams (BDD) for logic gates, which is used for constructing structurally synthesized BDDs (SSBDD). A new class of SSBDDs with multiple inputs (SSMIBDD) is proposed to reduce the size of collapsed fault sets. Experimental data show that the fault collapsing by the proposed method is more efficient than other strucural fault collapsing methods with comparative time cost are.

引用

页码：653 / 656

页数：4

共 25 条

[1] Adapa R, 2006, IEEE INT SYMP CIRC S, P815
[2] Accelerating diagnosis via dominance relations between sets of faults
Adapa, Rajsekhar
Tragoudas, Spyros
Michael, Maria K.
[J]. 25TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2007, : 219 - +
[3] Agrawal VD, 2003, INT TEST CONF P, P274, DOI 10.1109/TEST.2003.1270849
[4] AKERS SB, 1978, IEEE T COMPUT, V27, P509, DOI 10.1109/TC.1978.1675141
[5] Al-Assad H., 2002, P INT C VLSI, P72
[6] Fault equivalence identification in combinational circuits using implication and evaluation techniques
Amyeen, ME
Fuchs, WK
Pomeranz, I
Boppana, V
[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2003, 22 (07) : 922 - 936
[7] [Anonymous], 5 INT WORKSH BOOL PR
[8] [Anonymous], P TALLINN TU
[9] [Anonymous], 4 IASTED INT C MOD S
[10] BRYANT RE, 1986, IEEE T COMPUT, V35, P677, DOI 10.1109/TC.1986.1676819

← 1 2 3 →