Representation of strained gate-all-around junctionless tunneling nanowire filed effect transistor for analog applications

In this paper, we investigated gate-all-around silicon nanowire (NW)-based junctionless tunnel field effect transistor (FET) which is called junctionless tunnel NWPEI (JL-TNWFET) with the impact of variation of amount of uniaxial tensile strain on band-to-band tunneling (BTBT) injection and electrical characteristics. The tunneling model is first calculated for measurements of gate-controlled BTBT in the JL-TNWI-EI and is compared with the strained JL-TNWFET with similar technology parameters. The simulation results show that the JL-TNWFET have potential for low-operating-voltage application (V-dd $_amp_$lt; 0.4 V) and represent high I-ON/I-OFF ratio and steep subthreshold swing over many decade while encompassing high ON-state currents. Whereas, the strained JL-TNWFET due to thinner tunneling barrier at the source-channel junction which leads to the increase of carrier tunneling rate shows excellent characteristics with high ON-current, superior transconductance (g(m)) and cut-off frequency (f(T)). (C) 2016 Elsevier B.V. All rights reserved.