Optimization of Transfer Times in Pinned Photodiodes

An implantation scheme which enhances the readout speed of a silicon pinned photodiode (PPD) with large pixel length is presented. The basic PPD structure was developed for Time-of-Flight (TOF) distance measurement applications by the Fraunhofer IMS in Duisburg, Germany, and was fabricated in a standard 0.35 mu m CMOS process. The optimized design of this PPD introduces the possibility to improve the electron readout speed by changing the n-well configuration with a second well implantation. The local increase in doping concentration creates a designated electron path which utilizes the reset voltage of the readout node. This behaviour is shown by simulation and measurement results are presented.