Void free processing of flip chip on board assemblies using no-flow underfills

A consistent problem that has plagued the introduction of innovative no-flow underfill materials into volume flip chip onboard/in-package production is voiding of the underfill during processing. In addition to outgassing voids typically due to moisture and solvents in the substrate or outgassing of the underfill, voids are produced as a result of the squeeze flow experience by the underfill during chip placement. This paper presents a systematic development of optimal flip chip on board assembly process for no flow underfill materials presenting process parameters compatible with four commercially available no flow fluxing underfills. A novel hybrid process is developed that combines a capillary flow dynamic with no-flow fluxing underfills resulting in virtually a void free assembly process. Experiments are conducted to investigate the dispense pattern, placement speed and the impact of the placement process on interconnect yield further investigating the dispense pattern, placement force, and dwell time. A dispensed line pattern location and chip placement study is conducted to determine how voiding is affected by the position of the dispensed line in relation to the side of the die. The results of these experimental studies are used to select an optimal placement process for the materials. Reflow profile parameters are investigated using a parametric approach. The results of these initial studies are used to choose an optimal process for the materials. Test boards are assembled according to the optimal process for each material, and air to air thermal cycle, AATC, thermal cycling test is performed to qualify the assemblies. The newly developed edge patterned hybrid no-flow process has resulted in near void-free assemblies capable of passing 2000 cycles without an electrical failure for the -40 to 125 degreesC AATC reliability test.