Low cost efficient architecture for H.264 motion estimation

被引：9

作者：

López, S ^{[1
]}

Tobajas, F ^{[1
]}

Villar, A ^{[1
]}

de Armas, V ^{[1
]}

López, JF ^{[1
]}

Sarmiento, R ^{[1
]}

机构：

[1] Univ Las Palmas Gran Canaria, Dept Elect Engn & Control, Res Inst Appl Microelect, E-35017 Las Palmas Gran Canaria, Spain

来源：

2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/ISCAS.2005.1464612

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low cost VLSI architecture to compute the motion vectors required by the H.264/AVC video coding standard is presented in this paper. The possibility of avoiding motion estimation modes together with a novel partial distortion elimination strategy have been successfully incorporated in the proposed architecture, providing important savings in the power dissipation. As result, the implementation of the architecture in a low cost commercial FPGA is outlined in this paper, showing characteristics such as a reduced area occupation and an appropriate range of operation frequencies that make the architecture suitable for portable multimedia devices.

引用

页码：412 / 415

页数：4

共 9 条

[1] Efficient block size selection in H.264 video coding standard [J].