Phase interpolation technique based on high-speed SERDES chip CDR

被引：0

作者：

Lin, Meidong ^{[1
]}

Wen, Zhiping ^{[1
]}

Chen, Lei ^{[1
]}

Li, Xuewu ^{[1
]}

机构：

[1] BMTI, Beijing 100076, Peoples R China

来源：

PROCEEDINGS OF THE 2015 5TH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCES AND AUTOMATION ENGINEERING | 2016年 / 42卷

关键词：

phase interpolation; speed; serdes chips; the broadband rate Introduction;

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This design combines the advantages of CDR CDR circuit two structures PID and PI-based clock data is based on the structure of semi-digital dual loop recovery system. Using TSMC-0.25 mu m CMOS process to achieve the PLL design, the operating frequency range of 1.6-2.7GHz, and successfully applied a SERDES chip. Small footprint annular VCO wide frequency adjustment range, and can easily produce the CDR SerDes required multi-phase clock.

引用

页码：160 / 165

页数：6

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