Tag compression for low power in instruction caches

被引：0

作者：

Yang, Ming ^{[1
]}

Yu, Lixin ^{[1
]}

机构：

[1] Beijing Microelect Tech Inst, Coll Microelect, Beijing, Peoples R China

来源：

EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

As power consumption of the cache memory in modern processor designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing instruction cache power based on the operation of the Tag Compression Registers added in the cache system. The power savings show that, when the size of the Tag Compression Registers is properly fixed, the average saving on the power consumption of the instruction cache could be up to 64% compared with the traditional instruction cache structure.

引用

页码：837 / 840

页数：4

共 50 条

[1] Dynamic tag reduction for low-power caches in embedded systems with virtual memory
Petrov, Peter
Orailoglu, Alex
INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, 2007, 35 (02) : 157 - 177
[2] Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory
Peter Petrov
Alex Orailoglu
International Journal of Parallel Programming, 2007, 35 : 157 - 177
[3] Power efficient instruction caches for embedded systems
Suresh, DC
Najjar, WA
Yang, J
EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, 2005, 3553 : 182 - 191
[4] Instruction compression and encoding for low-power systems
Kadayif, I
Kandemir, MT
15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2002, : 301 - 305
[5] Low Power Optimization of Instruction Cache Based on Tag Check Reduction
Li, Quanquan
Bao, Lidan
Zhang, Tiejun
Hou, Chaohuan
2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 1269 - 1271
[6] Tag compression for low power in dynamically customizable embedded processors
Petrov, P
Orailoglu, A
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2004, 23 (07) : 1031 - 1047
[7] Power efficient embedded processor IP's through application-specific tag compression in data caches
Petrov, P
Orailoglu, A
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS, 2002, : 1065 - 1071
[8] Value compression to reduce power in data caches
Aliagas, C
Molina, C
Garcia, M
Gonzalez, A
Tubella, J
EURO-PAR 2003 PARALLEL PROCESSING, PROCEEDINGS, 2003, 2790 : 616 - 622
[9] Linked instruction caches for enhancing power efficiency of embedded systems
Ku, Chang-Jung
Chen, Ching-Wen
Hsia, An
Chen, Chun-Lin
MICROPROCESSORS AND MICROSYSTEMS, 2014, 38 (03) : 197 - 207
[10] RECAST: Boosting tag line buffer coverage in low-power high-level caches "for free"
Park, WH
Moshovos, A
Falsafi, B
2005 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 2005, : 609 - 616

← 1 2 3 4 5 →