Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator

Circuit intricacy, high-speed, low-power, small area requirement, and high resolution are crucial factors for highspeed and low-power applications like analog-to-digital converters (ADCs). The delay analysis of classical dynamic latch comparators is presented to add more insight of their design parameters, which effects the performance parameter. In this research, a new architecture of dynamic latch comparator is presented, which is able to provide high-speed, consumes low-power and requires smaller die area. The proposed comparator benefits from a new shared charge logic based reset technique to achieve high-speed with low-power consumption. It is shown by simulation and analysis that the delay time is significantly reduced compared to a conventional dynamic latched comparator. The proposed circuit is designed and simulated in 90 nm CMOS technology. The results show that, for the proposed comparator, the delay is 51.7 ps and consumes only 33.62 mu W power, at 1 V supply voltage and 1 GHz clock frequency. In addition, the proposed dynamic latch comparator has a layout size of 7.2 mu m x 8.1 mu m.