Efficiency of low-power design techniques in multi-gate FET CMOS circuits

被引：0

作者：

Pacha, C. ^{[1
]}

von Arnim, K. ^{[2
]}

Bauer, F. ^{[1
]}

Schulz, T. ^{[2
]}

Xiong, W. ^{[3
]}

San, K. T. ^{[3
]}

Marshall, A. ^{[3
]}

Baumann, T. ^{[1
]}

Cleavelin, C. -R. ^{[3
]}

Schruefer, K. ^{[1
]}

Berthold, J. ^{[1
]}

机构：

[1] Infineon Technologies, Munich, Germany

[2] Infineon Technol, Leuven, Belgium

[3] Text Instrument, Dallas, TX USA

来源：

ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Energy dissipation, performance, and voltage scaling of Multi-Gate FET (MuGFET) based CMOS circuits are analyzed using product-representative test circuits composed of 10k devices. The circuits are fabricated in a low power MuGFET CMOS technology, achieve clock frequencies of 370-500MHz at V-DD=1.2V, and operate down to the subthreshold region. Voltage scalabitity of MuGFET circuits is superior to sub-100nm planar CMOS circuits due to excellent short-channel effect control.

引用

页码：111 / +

页数：2

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