Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology

被引：6

作者：

Cilento, T. ^{[1
]}

Schenkel, M. ^{[1
]}

Yun, C. ^{[2
]}

Mishra, R. ^{[3
]}

Li, J. ^{[3
]}

Chatty, K. ^{[3
]}

Gauthier, R. ^{[3
]}

机构：

[1] Synopsys Switzerland LLC, CH-8050 Zurich, Switzerland

[2] Synopsys Inc, Mountain View, CA 94043 USA

[3] IBM Corp, Syst & Technol Grp, Semicond Res & Dev Ctr, Essex Jct, VT USA

来源：

MICROELECTRONICS RELIABILITY | 2010年 / 50卷 / 9-11期

关键词：

D O I：

10.1016/j.microrel.2010.07.132

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An ESD TCAD Workbench with a library of ESD and Latchup devices and circuits has been developed in a 32 nm bulk CMOS technology. The devices which were developed from process and layout information were calibrated to experimental results in the low current DC and high-current/high-temperature ESD regime. The failure currents of ESD devices correlated to the experimental data to within 15% and the failure location of the devices in TCAD were confirmed using failure analysis. (C) 2010 Elsevier Ltd. All rights reserved.

引用

页码：1367 / 1372

页数：6